1. Field of the Invention
The present invention relates, in general, to a semiconductor device and, more particularly, to a semiconductor device reduced in its occupying area. Also, the present invention is concerned with a process for fabricating the semiconductor device.
2. Description of the Prior Art
High integration of semiconductor device is accomplished with a great diminution in the area that is occupied by unit cell. An element of MOSFET, which occupies the most area in an integrated circuit of semiconductor device, is structured to have a source electrode connected with a substrate electrode in the integrated circuit.
In order to better understand of the background of the present invention, a description will be given for conventional technique with reference to some drawings.
FIG. 1A is a typical circuit diagram of PMOS in an integrated circuit. As shown in this figure, V.sub.DD is connected with a source electrode of PMOS and a substrate electrode while a drain of PMOS is grounded or connected with another electrode.
FIG. 1B is a typical circuit diagram of NMOS in an integrated circuit. As shown in FIG. 1B, V.sub.ss is connected with a source electrode of NMOS and a substrate electrode while a drain of NMOS is connected with V.sub.cc or another electrode.
Referring to FIG. 2, there is shown the PMOS of FIG. 1A fabricated oh a semiconductor device in a conventional technique. As shown in this figure, a semiconductor substrate 100 is provided with an N-well 10. Element isolation insulating layers 2 are formed on predetermined areas of the semiconductor substrate 1, so as to divide the semiconductor substrate into active regions and field regions. Then, a gate oxide 3 and a gate electrode 4 are in sequence formed on each of the active regions. Using this gate structure as a mask, P type impurities are implanted into the P-well, to form a source electrode 15A and a drain electrode 15B. Thereafter, impurities having the same type with the well, that is, P type impurities are implanted into a region isolated by the element isolation insulating layers, to form a substrate electrode 15C. Next, a blanket interlayer insulating layer 6 is formed over the resulting structure and then, subjected to selective etch, to form three contact holes which expose the source electrode 15A, the drain electrode 15B and the substrate electrode 15C. In order to interconnect the source electrode 15A with the substrate electrode 15C, a conductive wire 35A is formed filling the two contact holes. On the other hand, another conductive wire 35B is formed in order to come into contact with the drain electrode 15B.
As mentioned above, such conventional semiconductor device comes to has increased unit area because an additional substrate electrode is formed in an additional active region adjacent to the active region in which a source electrode and correspondingly, contact holes has to be formed for the contact with the substrate electrodes.
Consequently, it is virtually impossible to reduce the active region for source electrode with the prior technique in consideration of many hindrances, such as a reticle registration among a mask for source electrode, a mask for substrate electrode and a mask for gate electrode, a misalignment tolerance upon masking and a CD tolerance.